Integrated circuits are often formed using an application specific integrated circuit architecture, which tends to reduce the design costs of the integrated circuit by using predetermined logic blocks in a somewhat customized arrangement to produce an integrated circuit according to a customer's specifications. One aspect of such a customizable integrated circuit design is referred to as RRAM.
RRAM (Reconfigurable RAM) contains sets of memories of the same type that are placed compactly within a memory matrix. An RRAM, as the term is used herein, is a megacell that can be considered as a set of memories with built-in self testing and built-in self correction. RRAM also contains sets of embedded tools that are used for mapping arbitrary logical customer memory designs to the physical memories in the matrix. However, memory timing model generation tends to be a relatively difficult aspect of this type of RRAM design.
Each RRAM design typically contains several RRAMs. At the stage of memory placement during the design process, memories of the customer's netlist are mapped to the customizable standardized memories of the RRAMs. Then the RRAM megacells are configured in accordance with the resulting memory mapping. The configured RRAM is called a tiling netlist. After the tiling netlist is constructed, the issue of the customer memory timing model generation arises. In order to generate the timing model for some customer memories, we need to make the estimation of the tiling netlist timing.
The number of different memory mappings of the customer memories to the given RRAM is so high, that it is not reasonable to consider all of the different configurations of the memory mapping, and thus it is not reasonable to create the customer memory timing models for all of the different cases.
What is needed, therefore, is a learning method of timing estimation, that overcomes, at least in part, problems such as those described above.